ALICE3 TRK add the simplified-realistic OT barrel layout

Adds `TRKBase.layoutMLOT=kSimplifiedRealistic`: the ML is unchanged from
kSegmented, but the OT barrel is built from the parts it is actually made of
instead of solid silicon slabs. Geometry follows ALICE3 OT WP1 Material
(26.06.2025); all tunable dimensions are in constants::OT in Specs.h.

Module: cold plate, eight pure-silicon chips (2 in phi x 4 in z, read-out
edges facing the module edges), FPC, one ZIF connector, SMD capacitors over
the chip footprints and two mounting brackets, stacked flush about the chip
mid-plane. Stave: two module rows overlapping in phi and staggered in r,
with a cooling pipe between them and an end-of-stave FR4 readout card past
the last module.

Barrel: each layer is four quarter barrels, cut at mid-rapidity and on the
vertical plane so the region of the beam-pipe supports stays free of staves.
The stave count is no longer hard-coded; it is the smallest even number that
still leaves rowActiveOverlap of active double coverage at the layer radius.
The OT radii (440/615/793 mm) are chosen to improve overlap uniformity,
giving 30/42/54 staves per ring with 1.5-1.9 mm ofoverlap,
and keeping the outermost stave envelope clear of the OT shell.

Carbon fibre separation walls close the quarter barrels azimuthally and at
mid-rapidity (TRKServices::createOTBarrelWalls, thickness configurable via
TRKBase.otBarrelWallThickness). The layer envelopes are slotted along both
cuts so the walls run continuously in r rather than being interrupted at
every layer. Support half-rings carry the stave space frames.

New passive materials: carbon fibre, FPC (Kapton+Cu), LCP+Cu, BaTiO3, PEEK,
FR4 and copper.

Also needed to make the layout work end to end:
 - ProcessHits resolves stave/half-stave/module from the TGeo path, since
   the realistic OT builds them as assembly volumes whose CurrentVolOffID
   copy numbers all read 0;
 - ClustererSpec passed a file name where loadGeometry expects a prefix, so
   the clusterer could not open the geometry for any layout;
 - CheckDigitsTRK split VD/ML/OT on hard-coded chip indices that no longer
   matched the layout; they are now read from GeometryTGeo.

Author: bulukutlu

Detectors/Upgrades/ALICE3/TRK/README.md

@@ -15,8 +15,9 @@ Configurables for various sub-detectors are presented in the following Table:
 | Subsystem          | Available options                                       | Comments                                                         |
 | ------------------ | ------------------------------------------------------- | ---------------------------------------------------------------- |
 | `TRKBase.layoutVD` | `kIRIS4` (default), `kIRISFullCyl`, `kIRIS5`, `kIRIS4a` | [link to definitions](./base/include/TRKBase/TRKBaseParam.h) |
-| `TRKBase.layoutMLOT` | `kCylindrical`, `kSegmented` (default)     | `kSegmented` produces a Turbo layout for ML and a Staggered layout for OT                                                                 |
+| `TRKBase.layoutMLOT` | `kCylindrical`, `kSegmented` (default), `kSimplifiedRealistic` | `kCylindrical`: simple silicon tubes. `kSegmented`: Turbo ML + solid-module OT. `kSimplifiedRealistic`: same ML as `kSegmented`, but a detailed OT barrel (see below) |
 | `TRKBase.layoutSRV` | `kPeacockv1` (default), `kLOISymm` | `kLOISymm` produces radially symmetric service volumes, as used in the LoI |
+| `TRKBase.otBarrelWallThickness` | thickness in cm (default `0.2`) | Carbon fibre separation walls of the OT quarter barrels — side panels and mid-rapidity disks (`kPeacockv1` + `kSimplifiedRealistic`); `0` disables them. Does not cover the load-bearing outer shell (4 mm) |
 
 For example, a geometry with fully cylindrical tracker barrel (for all layers in VD, ML and OT) can be obtained by
 ```bash
@@ -26,7 +27,7 @@ o2-sim-serial-run5 -n 1 -g pythia8hi -m A3IP TRK FT3 TF3 \
 
 ## Custom Geometry Configuration
 
-The geometry of the ML and OT layers can be overridden by providing a custom plain-text configuration file via `TRKBase.configFile=filename.txt`. The parser interprets the file differently depending on the active `TRKBase.layoutMLOT` setting (`kCylindrical` or `kSegmented`).
+The geometry of the ML and OT layers can be overridden by providing a custom plain-text configuration file via `TRKBase.configFile=filename.txt`. The parser interprets the file differently depending on the active `TRKBase.layoutMLOT` setting (`kCylindrical`, or `kSegmented`/`kSimplifiedRealistic` which share the same syntax).
 
 ### General Syntax Rules
 * **Separators:** All columns **must** be separated by a single TAB (`\t`). Using spaces will result in a parsing error.
@@ -55,9 +56,9 @@ When `TRKBase.layoutMLOT=kCylindrical` is used, each layer requires a minimum of
 80.0	255.9	0.1
 ```
 
-### 2. Segmented Layout (`kSegmented`)
+### 2. Segmented / Simplified-Realistic Layout (`kSegmented`, `kSimplifiedRealistic`)
 
-When `TRKBase.layoutMLOT=kSegmented` is used, each layer requires a minimum of 5 base parameters to define the geometry. The parser distinguishes between Middle Layers (ML) and Outer Layers (OT) based on the sequential layer index.
+Both layouts use the same configuration-file syntax (only the OT geometry implementation differs). Each layer requires a minimum of 5 base parameters to define the geometry. The parser distinguishes between Middle Layers (ML) and Outer Layers (OT) based on the sequential layer index.
 
 * *(Note: The 5 base parameters map directly to: Inner Radius (`rInn`), Thickness (`thick`), Tilt Angle (`tiltAngle`), Number of Staves (`nStaves`), and Number of Modules per stave (`nMods`)).*
 
@@ -66,8 +67,9 @@ The first 5 valid lines are parsed as `TRKMLLayer` objects. These layers **requi
 * **Format:** `rInn` \t `thick` \t `tiltAngle` \t `nStaves` \t `nMods` \t `stagOffset` \t `[optional_mode]`
 
 **Outer Layers (OT) - Indices 5 and above**
-From the 6th valid line onwards, lines are parsed as `TRKOTLayer` objects. These layers do **not** have a staggering offset. The optional mode parameter shifts to the 6th column.
+From the 6th valid line onwards, lines are parsed as OT layer objects (`TRKOTLayer` for `kSegmented`, `TRKOTLayerRealistic` for `kSimplifiedRealistic`). These layers do **not** have a staggering offset. The optional mode parameter shifts to the 6th column.
 * **Format:** `rInn` \t `thick` \t `tiltAngle` \t `nStaves` \t `nMods` \t `[optional_mode]`
+* *(Note: for `kSimplifiedRealistic`, `nStaves` is recomputed internally from the average radius and stave width to guarantee the neighbour overlap; the value in the file is ignored for the OT.)*
 
 **Example for `kSegmented`:**
 
@@ -89,5 +91,27 @@ From the 6th valid line onwards, lines are parsed as `TRKOTLayer` objects. These
 80.0	0.01	0.0	56	22	1
 ```
 
+## Simplified-Realistic OT geometry (`kSimplifiedRealistic`)
+
+`kSimplifiedRealistic` keeps the ML layers identical to `kSegmented` but replaces the solid-silicon OT modules with a more detailed, but still simplified, description (`TRKOTLayerRealistic`). All tunable dimensions live in [`Specs.h`](./base/include/TRKBase/Specs.h) (`constants::OT`); values that depend on others are computed in the source.
+
+The geometry specification is based on [ALICE3 OT WP1 Material (26.06.2025)](https://indico.cern.ch/event/1562183/contributions/6580808/attachments/3093672/5480049/ALICE3_OT_WP1_Material_260625.pdf).
+
+**Module** — a flush stack about the chip mid-plane: cold plate (carbon fibre), 8 pure-silicon chips (2 in φ × 4 in z, dead zones facing the outer module edges), FPC (Kapton+Cu), one ZIF connector centred on a short edge, SMD capacitors over the chip footprints (skipping any under the connector), and two mounting brackets on the cold plate.
+
+**Stave** — two module rows overlapping in φ (so each row's dead zone is covered by the other row's sensor) and offset in r by `rowRadialStagger`, plus a cooling pipe between them. The rows straddle the stave frame origin, so a stave placed on the barrel circle is tangent at its own centre: every row-to-row radial step in the barrel — inside a stave and between neighbours — is then the same `rowRadialStagger`, in every layer.
+
+**End-of-stave card** — one readout PCB per stave (`constants::OT::eosCard`), mounted past the last module at the outer z end, coplanar with the two rows: a 120 × 80 mm, 1.5 mm FR4 board with four copper planes spread symmetrically through the thickness. The cards reach |z| ≈ 141 cm, just short of the OT barrel service disk.
+
+**Barrel** — each layer is built in **four parts**: two z-half-barrels (±η), each split azimuthally into two 180° halves. Both η half-barrels are cut on the **same vertical plane** (x = 0), so the region where the vertical beam-pipe supports run is free of staves over the whole barrel (the supports themselves are not in the geometry). Neighbouring staves overlap (≥ 1 mm active double-coverage); at the cut plane the two azimuthal halves instead leave a gap wide enough for the separation wall plus `barrelWallClearance` on each side. The stave count is the smallest even number that still meets the required overlap at the layer radius, so the OT radii (440, 615, 793 mm) are chosen at the top of a stave-count band, giving 30/42/54 staves per ring with 1.5-1.9 mm of overlap. The cooling pipe faces the larger radius on the inner two OT layers and the smaller radius on the flipped outer layer.
+
+**Separation walls** — the quarter barrels are closed on every side but the one carrying the end-of-stave cards (`TRKServices::createOTBarrelWalls`, `kPeacockv1` + `kSimplifiedRealistic`): radially by the ML/OT and outer carbon shells, azimuthally by a rectangular carbon fibre wall in the cut plane, and at mid-rapidity by a half disk at z = 0, one per quarter barrel.
+
+Both walls run **continuously** from one shell to the other: each OT layer envelope is a tube with a slot cut along the vertical cut plane *and* one at z = 0 (`TGeoCompositeShape`), so the walls pass through the layers instead of being interrupted by them, and what is left of each envelope is the four quarter barrels. The slots clear the walls by `barrelWallSlotMargin`; the staves stay `barrelWallClearance` away from them.
+
+Only the outer shell is load bearing, so it is the only 4 mm wall; the ML/OT shell is 2 mm and the side panels and mid-rapidity disks default to 2 mm via `TRKBase.otBarrelWallThickness`.
+
+The OT services (cables/cooling bundles, cold plates) are built by `TRKServices` for all layouts via `TRKBase.layoutSRV`.
+
 <!-- doxy
 /doxy -->

Detectors/Upgrades/ALICE3/TRK/base/include/TRKBase/Specs.h

@@ -125,6 +125,75 @@ constexpr double width{halfstave::width * 2};                             // wid
 constexpr double length{halfstave::length};                               // length of the stave
 constexpr int nRows{static_cast<int>(width / moduleMLOT::chip::pitchX)};  // number of rows in the stave
 constexpr int nCols{static_cast<int>(length / moduleMLOT::chip::pitchZ)}; // number of columns in the stave
+constexpr int nModulesPerRow{11};                                         // modules along z per row
+constexpr double interModuleGap{0.2 * mm};                                // z-gap between module FPCs
+
+// Component dimensions of the simplified-realistic OT stave
+namespace fpc
+{
+constexpr double length{116.8 * mm};    // z-extent
+constexpr double width{52.2 * mm};      // phi-extent
+constexpr double thickness{0.200 * mm}; // r-extent, Kapton+Cu stack
+} // namespace fpc
+namespace coldPlate
+{
+constexpr double length{116.8 * mm};  // z-extent
+constexpr double width{47.2 * mm};    // phi-extent
+constexpr double thickness{0.4 * mm}; // r-extent
+} // namespace coldPlate
+namespace connector
+{
+constexpr double width{25.0 * mm};    // phi-extent
+constexpr double length{10.0 * mm};   // z-extent
+constexpr double thickness{2.0 * mm}; // r-extent
+} // namespace connector
+namespace capacitor
+{
+constexpr double width{1.0 * mm};     // phi-extent
+constexpr double length{0.5 * mm};    // z-extent
+constexpr double thickness{0.3 * mm}; // r-extent
+constexpr int perChip{5};
+} // namespace capacitor
+namespace bracket
+{
+constexpr double length{10.0 * mm};   // z-extent
+constexpr double width{5.0 * mm};     // phi-extent
+constexpr double thickness{8.0 * mm}; // r-extent
+} // namespace bracket
+namespace coolingPipe
+{
+constexpr double rInner{0.4 * cm};
+constexpr double rOuter{0.5 * cm};
+constexpr double rLocalOffset{3.5 * cm}; // chip mid-plane to pipe axis, local r
+} // namespace coolingPipe
+namespace eosCard // end-of-stave readout card, one per stave
+{
+constexpr double length{120 * mm};         // z-extent
+constexpr double width{80 * mm};           // phi-extent
+constexpr double thickness{1.5 * mm};      // r-extent, FR4 + copper planes
+constexpr int nCopperLayers{4};            // copper planes, spread over the thickness
+constexpr double copperThickness{35 * mu}; // per copper plane (1 oz)
+constexpr double zGap{2.0 * mm};           // z-clearance from the last module
+} // namespace eosCard
+
+namespace supportRing // carbon fibre half-rings the stave space frames mount on
+{
+constexpr double radialHeight{30 * mm}; // r-extent of the ring cross-section
+constexpr double zWidth{12 * mm};       // z-extent of the ring cross-section
+constexpr double wallThickness{2 * mm}; // the ring is hollow
+constexpr double zClearance{1.0 * mm};  // z-clearance to the nearest wall and to the cooling pipe
+} // namespace supportRing
+
+constexpr double sensorThickness{moduleMLOT::silicon::thickness}; // pure-silicon chip (no metal stack)
+constexpr double interChipGap{0.2 * mm};                          // gap between chips within a module
+constexpr double rowActiveOverlap{1.0 * mm};                      // active overlap between the two rows of a stave
+constexpr double rowRadialStagger{2.0 * mm};                      // radial step between any two overlapping rows
+constexpr double halfBarrelChipGap{1.0 * mm};                     // gap between the two azimuthal half-barrels
+constexpr double barrelWallClearance{1.0 * mm};                   // clearance between a separation wall and the nearest stave
+constexpr double barrelWallSlotMargin{0.1 * mm};                  // clearance between a separation wall and its envelope slot
+constexpr double connectorZDepth{3.0 * cm};                       // connector inset from module short edge in z
+constexpr double bracketZDepth{3.0 * cm};                         // bracket inset from cold-plate short edge in z
+constexpr double barrelHalvesZGap{0.8 * cm};                      // z-gap between the two eta half-barrels
 } // namespace OT
 
 namespace apts /// parameters for the APTS response

Detectors/Upgrades/ALICE3/TRK/base/include/TRKBase/TRKBaseParam.h

@@ -30,6 +30,7 @@ enum eVDLayout {
 enum eMLOTLayout {
   kCylindrical = 0,
   kSegmented,
+  kSimplifiedRealistic,
 };
 
 enum eSrvLayout {
@@ -39,7 +40,8 @@ enum eSrvLayout {
 
 struct TRKBaseParam : public o2::conf::ConfigurableParamHelper<TRKBaseParam> {
   std::string configFile = "";
-  float serviceTubeX0 = 0.02f; // X0 Al2O3
+  float serviceTubeX0 = 0.02f;        // X0 Al2O3
+  float otBarrelWallThickness = 0.2f; // cm, carbon fibre separation walls of the OT quarter barrels, 0 disables them
   bool irisOpen = false;
   bool includeLowServices = false;